1. Field of the Invention
The invention relates to an apparatus and a method both of which give assistance in analyzing a reason of occurrence of deficiency in a RTL-input program such as a logic synthesizing tool or a logic testing tool.
2. Description of the Related Art
In designing logics in LSI, a hardware is described with a hardware description language (RTL language) of a register transfer level (RTL), and then, the RTL description data is input into a program called a logic synthesizing tool to fabricate a logic circuit, as suggested in Japanese Patent Application Publication No. 2003-85221, for instance.
Before inputting the RTL description data into a logic synthesizing tool, the RTL description data may be input into a program called a logic testing tool in order to check whether a logic circuit expressed in the RTL description data operates in a designed way or has contradictions therein. As an alternative, the RTL description data may be input into a program called a RTL checker to check a logic circuit expressed in the RTL description data.
In the specification, a program receiving RTL description data as input data, such as a logic synthesizing tool, a RTL checker and a logic testing tool, is called a RTL-input program.
An example of a RTL-input program is disclosed in Japanese Patent Application Publication No. 5-242191 (published September 1993). In accordance with the RTL-input program, RTL description data is analyzed to find deficiency in a logic circuit expressed with RTL description data.
Japanese Patent Application Publication No. 11-102385 (published April 1999) has suggested a system for giving assistance in designing LSI logics, including means for, when logic macro as a unit of a logic expressed with RTL language is divided into a plurality of macros, applying description relating to division to the RTL language, and analyzing the description relating to division to divide or unify the logic macro, and means for automatically defining input/output signals of the thus divided or unified macros.
When RTL description data is input into a RTL-input program in order to check or synthesize logics, the RTL-input program sometimes abnormally ends due to an internal error with unknown causes. The causes by which a RTL-input program abnormally ends are considered to be fault in RTL description data and/or bug in a RTL-input program.
However, there is a problem that it usually takes much time to identify the causes. The larger RTL description data is in scale, the more remarkable the problem is.
If a RTL-input program which abnormally ended is provided from a vendor, it would be necessary to provide RTL description data used when the RTL-input program abnormally ended, to the vendor in order to reproduce the error and identify causes for the error, which would be accompanied with another problem of security on RTL description data.